September 13-16, 2022
Dublin, Ireland + Virtual
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Friday, September 16 • 13:55 - 14:35
Design and Implementation of RISC-V Based LoRa Module - Mark Njoroge, University Of Cape Town

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The proliferation of the Internet of Things in both scale and complexity, alongside advances in optimised edge and fog system architectures, is driving an increasing need for low power consumption end nodes with greater computational capabilities. These distributed higher capacity nodes allow IoT infrastructures to minimise the power cost of data movement and increase real time response through increased edge data analytics. This presentation will showcase a prototype softcore RISC-V based LoRaWAN end node PCB design. By combining the reconfigurability and optimisation potential of a FPGA and RISC-V based architecture with a LoRa interface, the design contributes a novel option for use in solutions to the above. The design utilises the open source python framework LiteX to generate an SoC that contains the necessary core and peripherals to facilitate integration with a LoRa transeiver. The SoC is implemented on an ultra low power FPGA, providing access to both reconfigurable logic and a CPU for data analytics, and standard interfaces for 3rd party sensors. The whole design is integrated on a custom PCB in a USB dongle form factor. The resulting prototype can therefore be used as a peripheral for existing systems that may require additional compute power and IoT connectivity.

avatar for Mark Njoroge

Mark Njoroge

Student, University Of Cape Town
I am a young aspiring engineer with a keen interest in the world of Embedded Systems. I was born in Kenya and grew up in Botswana before moving to Cape Town for my undergraduate degree, which I completed in 2020, graduating with a BSc(Hons) Eng in Mechatronics at the University of... Read More →

Friday September 16, 2022 13:55 - 14:35 IST
Liffey Hall 2 (Level 1)