Open Source Summit Europe 2022

Embedded processors are increasingly equipped with powerful CPU cores. For mixed-criticality scenarios with multiple independent real-time appliances, this allows us to consolidate formerly distributed systems. This requires absence of unintended interaction between different computing domains, which can be achieved by exploiting virtualisation extensions of modern CPUs. Though providing strong isolation guarantees, virtualisation comes with an overhead, which may endanger global real-time properties of the system. The statically partitioning, Linux-based hypervisor Jailhouse addresses this challenge and strives at zero-overhead virtualisation, which maintains real-time capabilities of the platform by design. However, limitations of current architectures counter our architectural design goal of eliminating virtualisation overheads. In this talk, we extract architecture-independent common requirements on contemporary platforms to enable zero-trap virtualisation. We explore and compare the ARM, x86, and the RISC-V architecture, and inspect their architectural limitations for embedded zero-overhead virtualisation. We present common pitfalls and barriers of those platforms: Issues that have been addressed, that are being fixed and that need to be addressed in future.
With additional contributions from Wolfgang Mauerer, OTH Regensburg / Siemens AG.

This BoF provides an open forum for the embedded Linux community to ask questions and discuss issues with Yocto Project and OpenEmbedded principals.

The proliferation of the Internet of Things in both scale and complexity, alongside advances in optimised edge and fog system architectures, is driving an increasing need for low power consumption end nodes with greater computational capabilities. These distributed higher capacity nodes allow IoT infrastructures to minimise the power cost of data movement and increase real time response through increased edge data analytics. This presentation will showcase a prototype softcore RISC-V based LoRaWAN end node PCB design. By combining the reconfigurability and optimisation potential of a FPGA and RISC-V based architecture with a LoRa interface, the design contributes a novel option for use in solutions to the above. The design utilises the open source python framework LiteX to generate an SoC that contains the necessary core and peripherals to facilitate integration with a LoRa transeiver. The SoC is implemented on an ultra low power FPGA, providing access to both reconfigurable logic and a CPU for data analytics, and standard interfaces for 3rd party sensors. The whole design is integrated on a custom PCB in a USB dongle form factor. The resulting prototype can therefore be used as a peripheral for existing systems that may require additional compute power and IoT connectivity.

It is an exciting time for Linux on RISC-V, the open instruction set (ISA) that is quickly gaining critical mass. I will introduce the pieces needed to boot Linux on RISC-V including the Privileged Architecture, OpenSBI and U-Boot, and how that fits into the upcoming RISC-V Platform Specification. I will break down support for existing hardware and current upstreaming efforts. I will also discuss how the arch/riscv maintenance guidelines try to avoid unnecessary churn as the landscape of RISC-V extensions continues to evolve.

This BoF is a friendly space for people to gather and discuss the open RISC-V instruction set architecture and other open hardware efforts including open source cores and open source FPGA toolchains. Bring your questions and stories to this informal talk and learn more about the state of open hardware. RISC-V Ambassadors as well individuals from RISC-V International should be able to attend to both spark discussion and answer questions.