September 13-16, 2022
Dublin, Ireland + Virtual
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Note: The schedule is subject to change.

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IMPORTANT NOTE: Timing of sessions and room locations are subject to change.

Maciej Czekaj

Semihalf
Lead S/W Engineer

dr Maciej Czekaj is lead s/w engineer at Semihalf, specializing in embedded systems and networking applications. He has received his Comp. Sci. PhD program at AGH University (Kraków, Poland) on high-speed network acceleration. He is a contributor to the DPDK project (https://www.dpdk.org/) where he is a co-author of one of the first ARM64 Ethernet device drivers (VNIC on ThunderX ARM64 server). Recently, he has been working on Clang compiler technology for Xtensa DSP processors.

My Speakers Sessions

09:00 IST

DSP Welcomes Open Source - Xtensa HIFI DSP Support in Clang1 - Maciej Czekaj, Semihalf Liffey Meeting Room 2 (Level 1)